Electron mobility in strained Si channels is significantly higher than in bulk Si layers. Measured values at room temperature are about 3,000 cm.sup.2 /Vs as opposed to 400 cm.sup.2 /Vs in Si at the same electron density. Similarly, hole mobilities in strained SiGe layers with high Ge content (60% to 80%) have room temperature mobilities that are 5 times larger than in Si (800 cm.sup.2 /Vs compared to 150 cm.sup.2 /Vs). The implementation or use of such layers in high speed applications is thus expected to result in higher operating speeds than in state-of-the-art Si devices.
One problem, however, for high speed applications is that of the underlying substrate which may be conducting. GaAs microwave devices benefit from the fact that semi-insulating GaAs substrates are readily available. In Si technology, the normal ways to achieve insulating substrates is by resorting either to Separated by Implanted Oxygen (SIMOX) to form Si on insulator (SOI), Si on sapphire (SOS), or bond and etch back Silicon-On-Insulator (BESOI).
If one would start with any of these substrates in order to grow strained Si layers, one would have to grow a relaxed SiGe buffer first. In order to achieve such a buffer with low dislocation densities, the Ge content in the SiGe has to be graded over a distance that is about 1 .mu.m thick. U.S. Pat. No. 5,659,187 (Ser. No. 08/474,209) filed Jun. 7, 1995 by F. LeGoues et al. describes an incommensurate or relaxed top layer of low defect density single crystal material above a graded layer where the Ge content in SiGe is varied as a function of thickness. The thickness of the graded layer violates the requirement of a thin epitaxial layer on the insulator, which is the main advantage of SOI.
In U.S. Pat. No. 5,534,713 which issued Jul. 9, 1996 to K. E. Ismail and F. Stern and is assigned in part to the assignee herein, a plurality of epitaxial semiconductor layers are grown on a semiconductor substrate. One layer of the plurality of layers is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby an n channel field effect transistor may be formed with a channel under tension and a p channel field effect transistor may be formed with a channel under compression.
Therefore, there is a need for a technique capable of achieving Si channels under tensile strain, relaxed SiGe layers, and SiGe channels under compressive strain, all standing on an insulating substrate.